1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) device, and more particularly, to a method of fabricating a liquid crystal display device.
2. Discussion of the Related Art
In general, a liquid crystal display (LCD) device includes two substrates, which are spaced apart and facing each other, and a liquid crystal layer interposed between the two substrates. Each of the substrates includes an electrode, and the electrodes of each substrate are also facing each other. A voltage is applied to each electrode, and thus an electric field is induced between the electrodes. An alignment of the liquid crystal molecules is changed by varying an intensity or direction of the electric field. The LCD device displays a picture by varying transmissivity of the light according to the arrangement of the liquid crystal molecules.
The related art LCD device will be described hereinafter more in detail with reference to FIG. 1.
FIG. 1 is an expanded perspective view illustrating the related art liquid crystal display device. The related art LCD device 1 has first and second substrates 5 and 22, which are spaced apart from and facing into each other, and also has liquid crystal 15 interposed between the first substrate 5 and the second substrate 22.
A black matrix 6, a color filter layer 7, and a common electrode 9 are subsequently formed on the inside of the first substrate 5 (i.e., the side facing the second substrate 22). The black matrix 6 has an opening. The color filter layer 7 corresponds to openings in the black matrix 6 and includes three sub-color filters of red (R), green (G), and blue (B). The common electrode 9 is transparent. The first substrate 5 including the black matrix 6, the color filter layer 7, and the common electrode 9 is commonly referred to as a color filter substrate.
A plurality of gate lines 12 and data lines 34 are formed on the inner surface of the second substrate 22 (i.e., the side facing the first substrate 5). The gate lines 12 and the date lines 34 cross each other and define a pixel area P. A thin film transistor T, as a switching element, is formed at the crossing of the gate line 12 and the data line 34. The thin film transistor T includes a gate electrode, a source electrode and a drain electrode. A plurality of the thin film transistors is arranged in a matrix form and connected to the gate and data lines. A pixel electrode 56, which is connected to the thin film transistor T, is formed in the pixel area P. The pixel electrode 56 corresponds to the sub-color filter, and is formed of a transparent conductive material such as indium-tin-oxide (ITO). The second substrate 22, which includes the thin film transistors T and the pixel electrodes 56 arranged in the matrix form, is commonly referred to as an array substrate.
In operating the LCD device, a scanning pulse is applied to the gate electrode of the thin film transistor T through the gate line 12 and a data signal is applied to the source electrode of the thin film transistor T through the data line 34.
The LCD device is driven by the electrical and optical effects of the liquid crystal. The liquid crystal is a dielectric anisotropic material having the characteristic of spontaneous polarization. When a voltage is applied, the liquid crystal forms a dipole by the spontaneous polarization, and thus molecules of the liquid crystal are arranged by an electric field. Optical modulation occurs from the optical characteristics of the liquid crystal, which vary according to the arrangement of the liquid crystal. Images of the LCD device are produced by controlling transmittance of the light due to the optical modulation.
FIG. 2 illustrates a plane view of an array substrate for a LCD device according to the related art. In FIG. 2, a gate line 12 and a data line 34 on a substrate 22 cross each other and define a pixel area P. A thin film transistor T is formed as a switching element at each crossing of the gate and data lines 12 and 34. A gate pad 10 is formed at one end of the gate line 12, and a data pad 36 is formed at one end of the data line 34. A gate pad terminal 58 and a data pad terminal 60, which have an island shape and are formed of a transparent conducting material, overlap the gate pad 10 and the data pad 36, respectively.
The thin film transistor T includes a gate electrode 14 that is connected to the gate line 12 and receives scanning signals, a source electrode 40 that is connected to the data line 34 and receives data signals, and a drain electrode 42 that is spaced apart from the source electrode 40. The thin film transistor T further includes an active layer 32 between the gate electrode 14 and the source and drain electrodes 40 and 42. A metal pattern 38 of an island shape overlaps the gate line 12.
A pixel electrode 56 is formed in the pixel area P and is connected to the drain electrode 42. The pixel electrode 56 is also connected to the metal pattern 38. The gate line 12 and the metal pattern 38 function as first and second storage capacitor electrodes, respectively, and form a storage capacitor Cst with a gate insulating layer (not shown) disposed between the gate line 12 and the metal pattern 38.
Although not shown in the figure, an ohmic contact layer is formed between the active layer 32 and the source and drain electrodes 40 and 42. The active layer 32 is formed of amorphous silicon, and the ohmic contact layer is formed of doped amorphous silicon. A first pattern 35 and a second pattern 39, which include the amorphous silicon and the doped amorphous silicon, are formed under the data line 34 and the metal pattern 38, respectively.
The array substrate of FIG. 2 is fabricated by using four masks.
FIGS. 3A to 3G, FIGS. 4A to 4G, and FIGS. 5A to 5G illustrate the process steps of fabricating an array substrate using four masks, and correspond to cross-sectional views taken along line III-III, line IV-IV, and line V-V of FIG. 2, respectively.
As illustrated in FIGS. 3A, 4A and 5A, a gate line 12, a gate electrode 14, and a gate pad 10 are formed on a transparent insulating substrate 22 by depositing a first metal layer and patterning the first metal layer through a first photolithography process using a first mask. The gate line 12, the gate electrode 14, and the gate pad 10 are formed of a metal material such as aluminum (Al), an aluminum alloy, molybdenum (Mo), tungsten (W), and chromium (Cr). The gate line 12, the gate electrode 14, and the gate pad 10 made of aluminum or an aluminum alloy may be formed of a double layer including molybdenum or chromium.
Next, a gate insulating layer 16, an amorphous silicon layer 18, a doped amorphous silicon layer 20, and a second metal layer 24 are subsequently deposited on the substrate 22 including the gate line 12, the gate electrode 14, and the gate pad 10. The gate insulating layer 16 is formed of an inorganic insulating material, such as silicon nitride (SiNx) and silicon oxide (SiO2), while the second metal material 24 is formed of one of chromium, molybdenum, tungsten and tantalum (Ta).
As illustrated in FIGS. 3B, 4B, and 5B, a photoresist layer 26 is formed on the second metal layer 24 by coating photoresist. A second mask 70, which has a transmitting portion A, a blocking portion B, and a half transmitting portion C, is disposed over the photoresist layer 26 spacing apart from the photoresist layer 26. The half transmitting portion C corresponds to the gate electrode 14. The photoresist layer 26 may be a positive type, and a portion exposed to the light is developed and removed. Subsequently, the photoresist layer 26 is exposed to the light. The photoresist layer 26 corresponding to the half transmitting portion C is exposed less than the photoresist layer 26 corresponding to the transmitting portion A.
As illustrated in FIGS. 3C, 4C, and 5C, the exposed photoresist layer 26 of FIGS. 3B, 4B, and 5B is developed, and a photoresist pattern 26a is formed. Because of different transmittances of the portions of the second mask 70, the photoresist pattern 26a has different thicknesses. A first thickness of the photoresist pattern 26a corresponds to the blocking portion B of FIGS. 3B, 4B, and 5B, and a second thickness of the photoresist pattern 26a, which is thinner than the first thickness, corresponds to the half transmitting portion C of FIGS. 3B, 4B, and 5B.
As illustrated in FIGS. 3D, 4D, and 5D, the second metal layer 24, the doped amorphous silicon layer 20, and the amorphous silicon layer 18 of FIGS. 3C, 4C, and 5C exposed by the photoresist pattern 26a are removed. Thus, a source and drain pattern 28, a data line 34 of FIG. 2, a data pad 36, a doped amorphous silicon pattern 30a, and an active layer 32 are formed. The second metal layer 24 of FIGS. 3C, 4C, and 5C is etched by a wet etching method, and the doped amorphous silicon layer 20, and the amorphous silicon layer 18 of FIGS. 3C, 4C, and 5C are patterned by a dry etching method. The source and drain pattern 28 is formed over the gate electrode 14, and is connected to a data line 34 of FIG. 2, which extends vertically in the context of the drawing. The doped amorphous silicon pattern 30a and the active layer 32 have the same shape as the source and drain pattern 28.
At this time, a metal pattern 38 of an island shape is also formed over the gate line 12. A first pattern 35 and a second pattern 39, which include the amorphous silicon layer and the doped amorphous silicon layer, are formed. The first pattern 35 is located under the data line (not shown), and the data pad 36 and the second pattern 39 is positioned under the metal pattern 38.
Next, as illustrated in FIGS. 3E, 4E, and 5E, the second thickness of the photoresist pattern 26a is removed through an ashing process, so that the source and drain pattern 28 is exposed. Here, the photoresist pattern 26a of the first thickness is also partially removed, and the first thickness of the photoresist pattern 26a is thinned. Additionally, edges of the photoresist pattern 26a are removed, and the metal patterns 28, 36, and 38 are exposed.
As illustrated in FIGS. 3F, 4F, and 5F, the source and drain pattern 28 and the doped amorphous silicon pattern 30a of FIG. 3E, which are exposed by the photoresist pattern 26a of FIG. 3E, are etched. Thus, source and drain electrodes 40 and 42 and an ohmic contact layer 30 are formed, and the active layer 32 is exposed. The exposed active layer 32 between the source and drain electrodes 40 and 42 becomes a channel of a thin film transistor. The source and drain electrodes 40 and 42 are spaced apart from each other. A region between the source and drain electrodes 40 and 42 corresponds to the half transmitting portion C of the second mask 70 of FIG. 3B. If the source and drain pattern 28 of FIG. 3E is formed of molybdenum (Mo), the source and drain pattern 28 and the doped amorphous silicon pattern 30a of FIG. 3E can be removed using a dry etching method at once. However, if the source and drain pattern 28 is formed of chromium (Cr), the source and drain pattern 28 is etched by a wet etching method, and then the doped amorphous silicon pattern 30a is removed by a dry etching method.
As stated above, the source and drain electrodes 40 and 42, the data line, the data pad 36, the metal pattern 38, the ohmic contact layer 30, and the active layer 32 are formed through a second photolithography process using the second mask of FIGS. 3B, 4B, and 5B.
Next, the photoresist pattern 26a is removed, and a passivation layer 46 is formed on the data line, the source and drain electrodes 40 and 42, the data pad 36, and the metal pattern 38 by coating a transparent organic material, such as benzocyclobutene (BCB) and acrylic resin, or depositing an inorganic material, such as silicon nitride (SiNx) and silicon oxide (SiO2). The passivation layer 46 is patterned with the gate insulating layer 16 through a third photolithography process using a third mask, and a drain contact hole 48, a storage contact hole 50, a gate pad contact hole 52, and a data pad contact hole 54 are formed. The drain contact hole 48, the storage contact hole 50, the gate pad contact hole 52, and the data pad contact hole 54 expose the drain electrode 42, the metal pattern 38, the gate pad 10, and the data pad 36, respectively. Here, the storage contact hole 50 exposes a sidewall of the metal pattern 38.
As illustrated in FIGS. 3G, 4G, and 5G, a pixel electrode 56, a gate pad terminal 58, and a data pad terminal 60 are formed on the passivation layer 46 by depositing a transparent conductive material, such as indium-tin-oxide (ITO) and indium-zinc-oxide (IZO), and patterning the transparent conductive material through a fourth photolithography process using a fourth mask. The pixel electrode 56 is connected not only to the drain electrode 42 through the drain contact hole 48, but also to the metal pattern 38 through the storage contact hole 50. The gate pad terminal 58 and the data pad terminal 60 are connected to the gate pad 10 and the data pad 36 through the gate pad contact hole 52 and the data pad contact hole 54, respectively.
As mentioned above, the array substrate is fabricated through the photolithography processes using masks. The photolithography process includes several steps of cleaning, coating a photoresist layer, exposing through a mask, developing the photoresist layer, and etching. Therefore, a fabricating time, costs, and failure can be decreased by reducing the number of the photolithography process.